FPGA
Edge-based applications necessitate low latency and power efficiency
Many edge-based applications necessitate low latency and power efficiency, alongside the ability to process substantial amounts of data from sensors and cameras. Our team possesses extensive proficiency in utilizing FPGA devices, which enable the execution of such computationally demanding systems.
Our expertise lies specifically in computer vision and deep learning applications, specializing in developing FPGA accelerators for machine learning inference, computer vision, and image processing algorithms. These accelerators empower the creation of real-time, low-latency, and power-efficient systems. In addition, our expertise in software design enables us to create comprehensive solutions when needed.
Furthermore, in the field of automotive SoC development, we can establish a design flow and deliver designs in accordance with relevant industry standards. For a glimpse into some of our past projects, please refer to the provided references.
AMD Partner
As a Select Certified Member of the AMD Adaptive Computing Partner Program, we have a track record of designing programmable logic/software-optimized solutions for AMD SoC (System on Chip), which is considered a preferred platform.
EVS and AMD (Xilinx) have a longstanding partnership focused on leveraging the potential of FPGA and AMD Zynq SoC devices for Computer Vision in the Automotive industry. This collaboration led to crafting FPGA IPs for advanced functionalities such as Lane Departure Warning, Pedestrian Detection, and Vehicle Detection. This partnership enabled the distribution of EVS FPGA IPs and provision of services to automotive customers.
Services
FPGA servicesoffered by EVS
Analysis
- Concept and feasibility studies
- Architecture definition and optimal PL/PS partitioning
- Resource occupation, latency, bandwidth, and power estimation
- Bit-accurate golden model implementation
- Rapid prototyping
Design
- RTL development in VHDL/Verilog
- Design optimization (for speed/area/power)
- LINT and code reviews, refactoring, assessments
- FPGA to ASIC migration
- Static timing analysis and timing closure
Verification
- Metric driven verification
- Formal verification, assertions, static property checking
- Code and functional coverage (UVM, OVM)
- Constrained random stimulus generation
- Regression testing and fault injection
- Bus transactions simulation via BFM
OS/Firmware
- Integration of device drivers and development of kernel modules for our IP
- We employ various abstractions such as BareMetal and Linux Systems, depending on the specific application at hand
Examples
FPGA IP Core
NPU
Full-custom Neural Processing Unit and its related toolchain: Fully programmable inference acceleration engine (dedicated instruction set), Data/parameter integer quantization, Support for the state of the art network models.
Detecto
Lightweight and scalable object detector based on Histogram of Oriented Gradient (HOG) and Support Vector Machines (SVM).
VDET
Object detector based on local binary pattern (LBP) feature and cascade of boosted classifiers (Viola-Jones like). Applications: vehicle/face detection.
DPM
Object detector based on Deformable Part Models (DPM). It uses a star-structured part-based model, defined by root filters and a set of part-based filters with associated deformation models.
RL-LMD
Rear Looking Lane Marking Detection: Bird eye view working space, Robust to shadows and light changes, Straight lane model fitting based on Hough Transform.
FL-LMD
Forward Looking Lane Marking Detection: Lane marking detection based on image processing and pattern search, Hyperbolic lane model fitting based on RANSAC, Lane model tracking based on Kalman Filter.
Gaussian Filter
Image noise reduction by convolving the input image with a 2D Gaussian kernel. Optimized based on separable and symmetric masks.
Median Filter
Non-linear filtering for removing impulsive (salt and pepper) noise based on median operator (3x3 or 5x5).
Histogram stretching
It enhances the contrast of the image by stretching its histogram and using the entire intensity range.
Edge detector
It computes the edge map by using Sobel operators. Thinning is applied to obtain 1-pixel thick contour, Automatic cutoff using Otsu method.
Image segmentation
It returns a binary map separating background and foreground regions. Under the hypothesis of bimodal image. The segmentation threshold is adaptive and computed analyzing to the image histogram.
Corner extractor
Based on the Harris operator, it extracts the corner points by detecting significant changes of the gradient intensity along two directions. It returns a set of corner coordinates and the corresponding degrees of confidence.
Image warping
It applies a 2D geometrical spatial transformation to the image coordinates and re-samples the grid. It processes the image in two steps: backward mapping and bilinear interpolation. The warping model can be based on 6 (affine) or 8 (projective) parameters.
Image pyramid generator
It is a fully programmable IP block returning a pyramid of images at different scale in external memory: up/down scaling, ROI cropping/padding capability, bilinear interpolation, anti-aliasing.
Stereo vision core
Stereo vision engine for real-time three-dimensional depth data extraction based on Census Transform: multi-resolution approach, subpixel refinement, left-right cross-check.
Technologies
Technologies we use
This brief compilation showcases our expertise, highlighting a diverse array of technologies that we employ in our daily operations to craft effective solutions and attain desired outcomes.
Deep learning frameworks
Pytorch
TensorFlow
TensorFlow Lite
ONNX
Keras
TorchScript
Deep learning frameworks
Pytorch
TensorFlow
TensorFlow Lite
ONNX
Keras
TorchScript
Our preferred image and media annotation tool
V7
HPC workload manager
Slurm Workload Manager
Preferred frameworks for 3D modeling
Blender
Viewer for neural network, deep learning and machine learning models
Netron
FPGA Design & Verification
AMD Vivado
AMD Vitis
Cocotb
Mentor ModelSim
VHDL
FPGA Design & Verification
AMD Vivado
AMD Vitis
Cocotb
Mentor ModelSim
VHDL
Programming languages
C++
Python
Tcl/Tk
MathLab
Programming languages
C++
Python
Tcl/Tk
MathLab
Libraries we often rely on for our solutions
OpenCV
QT
Gstreamer
ZeroMQ
OpenGL
Libraries we often rely on for our solutions
OpenCV
QT
Gstreamer
ZeroMQ
OpenGL
Operating Systems
Linux
Linux Embedded
Operating Systems
Linux
Linux Embedded
Front End
TypeScript
React JS
Bootstrap
Material UI
Front End
TypeScript
React JS
Bootstrap
Material UI
Back End
Node JS
Express JS
Flask
OpenAPI
Back End
Node JS
Express JS
Flask
OpenAPI
Database
MongoDB
MySQL
Elasticsearch
PostgreSQL
Database
MongoDB
MySQL
Elasticsearch
PostgreSQL
Cloud Infrastructure
Firebase
Microsoft Azure
Cloud Infrastructure
Firebase
Microsoft Azure
Mobile
Flutter
React Native
Mobile
Flutter
React Native
Testing
Playwright
Jest
Testing
Playwright
Jest
DevOps and CI/CD
Docker
Kubernetes
Jenkins
JFrog Artifactory
DevOps and CI/CD
Docker
Kubernetes
Jenkins
JFrog Artifactory
Source Code Management
GIT
Bitbucket
GITHUB
Source Code Management
GIT
Bitbucket
GITHUB
Case Studies
Related projects
Within our portfolio, we have a multitude of diverse FPGA projects, with a primary focus on the automotive industry. These endeavors serve as compelling evidence of our team’s proficiency in effectively addressing intricate challenges, and consistently attaining predefined goals within established timelines. Such achievements owe their success to the combined expertise and dependability of our engineering team, coupled with a development and verification process that has undergone thorough scrutiny, validation, and enhancement over the course of several years. By leveraging these strengths, we deliver tangible value to our esteemed clientele through diminished project risk factors, adherence to budgetary constraints, and accelerated time-to-market for novel products.
Automotive
Embedding DMS/OMS
EVS’ prowess in high performance embedding and image processing, specializing in FPGA and ASIC design technology, finds good examples in the deep strategic relationship with Seeing Machines, which extends back to 2015.
Automotive
Detecto IP core
Detecto is an IP core designed by EVS that speeds up object detection tasks in programmable logic. Detecto is optimized for AMD SoC.
Automotive
Automotive Driving Assistance Development Kit
The FPGA design of driving assistance features, such as Lane Departure Warning, Pedestrian Detection and Vehicle Detection and their integration into an automotive driving assistance development platform based on AMD Zynq-7000 SoC and Zynq UltraScale+ MPSoC devices.
Transports
DynaPCN: The People Counter
DynaPCN is a compact and autonomous passenger counting device, designed by Eurotech and based on stereo vision. It is designed for mounting above bus and train doorways and can also be used to count people as they enter or leave buildings or any area with restricted access.